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HIPEAC
- 09 Jun 2007
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Full Name: | High-Performance Embedded Architectures and Compilers | |
Basic data: | Type of the project: | EU IST FP6 project, Network of Excellence |
| IST SO: | Embedded systems | |
| Project Reference: | 004408 | |
| Launch: | September 2004 | |
| Duration: | 48 months | |
| Consortium: | 15 partners from 11 countries | |
| Coordinator: | Universitat Politecnica de Catalunya, Spain | |
Webpage | http://www.hipeac.net/ | |
Description: | HiPEAC addresses the design and implementation of high-performance commodity computing devices in the 10+ year horizon, covering both the processor design, the optimising compiler infrastructure, and the evaluation of upcoming applications made possible by the increased computing power of future devices. The objectives of HiPEAC are to ensure the visibility of European institutions in the high performance embedded marked, and to promote the integration of research efforts in a common direction. HiPEAC will also provide the means for easy collaboration among members, and rapid dissemination of knowledge among the community, as well as strengthening the relationships between academia and European industry. HiPEAC brings together the leading European experts in computer architecture, coordinating -for the first time- their research effort. HiPEAC will build up European strength by spreading knowledge and expertise to engineers and students, and by transferring this expertise to industry, with the goal of making Europe the worldwide leader in high-performance embedded processor architectures. The end target is to create a virtual center of excellence in high-performance compilers and architectures for embedded processors. This center will gather the world's largest critical mass of researchers, generate world-leading results in embedded architectures, and offer the best discussion forums on our topics of influence, becoming a focal point in the fields of computer architecture and optimising compilers at the maximum level. | |
| Relevance to HYDRA: | HiPEAC integrates the newest knowledge in the research area of high-performance embedded processor architectures on academic and industrial level. This knowledge may be helpful in the phase of HYDRA technical design. | |